Analysis and Design of High Speed Power Efficient Pipelined ADC

  • Priyesh P. Gandhi


This paper presents analysis and design of high speed power efficient Pipelined ADC. The enthusiasm for High speed, medium objectives, low control ADCs is satisfied by various ADC structures like crumbling, sub ranging, pipeline, etc. Of these, pipeline configuration has exhibited to be the best for applications, for instance, propelled correspondence structures, data acquisition systems and video structures. The Pipelined ADC offer appealing blend of quick, high-precision and low control use, which make it the most overwhelming and profitable data converters among others. Thus, the objective of this work is to structure and complete a low power, medium-objectives (8-10bits) quick pipeline ADC in submicron CMOS development. A High Speed 10-piece 1000MS/s pipeline ADC was organized and realized in a 0.18?m CMOS Technology. Principal structure squares of the pipeline ADC are test additionally, hold, sub-ADC, sub-DAC and enhancer. Dynamic Latch Comparator is used to extend the change rate and decline the general power dispersal of ADC.