Multidirectional Reconfigurable Router for Network on Chip (NoC)

  • Dr. Himani Mittal Gupta
  • Dr. Yogendera Kumar


In N.O.C links or various interconnections power dissipation contribute to major fraction. In fact, as technology shrinks, the power contribute of NoC links starts to compete with that of NoC routers. In this paper, we design linkI , II , III with the help of MUX gating and various encoding techniques to reduce both power dissipation and energy consumption of NoC links.In this work,we try to reduce power consumption in NoC links in three ways : Mux gating ,coding and encoding techniques .
This paper analyzes the behavior of Link design I,II,III in the highly structured environment of a network-on-chip (NoC).. After simulations , we obtain a reduction in total power dissipation and number of bit transitions up to 35% and 40%, respectively, without any significant degradation in terms of both performance and silicon area.